As semiconductor processes continue to scale downwards, e.g., shrink, the desired spacing between features (i.e., the pitch) also becomes smaller. To this end, in the smaller technology nodes it becomes ever more difficult to fabricate features due to the critical dimension (CD) scaling and process capabilities.
For example, in the fabrication of FinFET structures, single diffusion breaks become very attractive in standard cell scaling. The processes for fabricating the single diffusion breaks, though, are very challenging in advanced technologies. By way of illustration, conventionally, multiple Rx regions in a semiconductor integrated circuit include arrays of parallel extending fins having distal ends abutting the edges of each Rx region. The fin arrays are terminated by dummy gates, which extend laterally across the distal ends of the fins at the edges of the Rx regions. The dummy gates are used to induce symmetrical epitaxial growth of source/drain regions (S/D regions) on the end portions of the fins located between the dummy gates and adjacent active gates.
To fabricate the single diffusion break, a deep trench undercut adjacent to the source and drain epitaxial regions is provided by removing the dummy gate structure (poly material). The deep trench etch undercut damages or removes portions of the epitaxial source and drain regions. This results in smaller source/drain epitaxial volume and electrical contact area compared to that of the source and drain regions located between active gates. The smaller source and drain region volume and contact area can lead to greater contact resistance and degrade device performance.